1. Technical Field
The present invention relates generally to generating clock signals for integrated circuits and in particular to multiplying clock signals within an integrated circuit. Still more particularly, the present invention relates to a fully digital clock multiplier providing N/M clock frequency multiplication while maintaining precise duty cycles.
2. Description of the Related Art
Clock multipliers are widely employed in modern semiconductor devices. A common implementation involves a phase lock loop (PLL), using analog circuits such as a phase/frequency detector and a charge pump to bias a voltage controlled oscillator (VCO) such that a divided version of the VCO matches a reference clock. Because they require analog components, however, these multipliers cannot be built from a purely digital library, utilizing processing technology optimized for purely digital circuits. Moreover, such multipliers have long acquisition times, usually on the order of hundreds to thousands of clock cycles.
A technique employed for digitally doubling a clock involves XORing a reference clock signal with the same signal delayed by 90 degrees (one quarter clock cycle) as shown in FIG. 5A. The XORed output will have a frequency which is twice the frequency of the reference clock signal, as depicted in FIG. 5B. However, ordinary circuit delay elements vary widely with changing operating parameters such as voltage, temperature, and variances in integrated circuit processing. As a result, the clock duty cycle will vary widely for the doubled clock, as illustrated in FIGS. 5C and 5D.
The XOR method of clock doubling described is also limited to obtaining a frequency which is twice the reference clock frequency. Thus, even if a method of adding a precise amount of delay (90 degrees) between the XOR inputs were devised, the frequency range achievable would be limited. At best, the frequencies which could be obtained from such a mechanism would be some power of two times the reference clock frequency.
It is desirable, therefore, to provide a clock multiplier which may be implemented with only digital components and fabricated using only digital processes. It is also desirable to provide a clock multiplier capable of producing a frequency which is any whole number or fractional multiple of the input or reference clock frequency. It would also be advantageous to obtain a precise duty cycle in the output clock signal.